The goal of High Performance Spaceflight Computing activities is to develop a next-generation flight computing system addressing the computational performance, energy management, and fault tolerance needs of NASA missions through 2030 and beyond.
Space-based computing has not kept up with the needs of current and future NASA missions. The objective of the High Performance Spaceflight Computing (HPSC) project is to develop a next-generation flight computing system addressing the computational performance, energy management, and fault tolerance needs of NASA missions through 2030 and beyond.
NASA’s Office of the Chief Technologist Strategic Technology Roadmaps call out the need for more capable flight computing:
• (TA04) Advances in high performance low power onboard computers are central to more capable space robotics.
• (TA05) Many of the complex [objectives of] future missions . . . can be mitigated by making decisions closer to the platform . . . this goal is coupled with the need for increased autonomy and flight computing.
• (TA09) Landing challenges include highly capable and low power on-board dedicated compute element….
• (TA11) Pinpoint landing, hazard avoidance, rendezvous-and-capture, and surface mobility are directly tied to the availability of high-performance space-based computing.
The technology being advanced is the HPSC chiplet—a multicore rad-hard flight processing chip for use within a general-purpose processor—conceived in a reference architecture as a dual quad-core building block, with provisions for extensibility and interoperability with other computing devices, and with native architectural support for power scaling and energy management, as well as hosting of software-based fault tolerance methods.
The Boeing Co. has been contracted to develop and provide the chiplet hardware processor, associated system software and software development environment, an evaluation board and a software simulator/emulator. Boeing is also expected to provide key design documentation as well as technical specifications with performance information (estimated or measured) of the chiplet during the design and fabrication phase.
|Principal Technologist||Program Manager|
|Steve Horan (firstname.lastname@example.org)||Richard Doyle (email@example.com)|